The present invention relates generally to the field of microprocessors; more particularly, to cache memories and cache memory hierarchies for use in improving the performance of processor-based computer systems.
The push for higher performance levels in modern microprocessors has led to the development of new optimization techniques in architectural extensions. These features include speculation, predication, larger register files, a register stack, and an advanced branch architecture. Proposed architectural extensions provide for 64-bit capabilities. One way that new architectural features can enable high performance in future processor implementations is in the handling of high performance procedural calls and returns, which require all parameters between the calling and called procedures to be passed through registers. In traditional architectures, procedure calls retard performance since registers must be spilled and filled repeatedly. By way of example, as nested and recursive calls are encountered in a program, additional registers may need to be allocated to the parameter stack, which will eventually overflow the physical register file size. This condition has created a need for new procedures and apparatus to communicate register usage to the processor. It is desirable in new architectural extensions to avoid the unnecessary spilling and filling of registers at procedure call and return interfaces.
The present invention provides a processor for executing a code sequence that includes multiple function calls comprising a register file having a predetermined size and a means for allocating sets of registers on a per-function call basis. Additionally, a reserve storage area is included and a means for saving a particular set of registers in the reserve storage area responsive to a function call that would overflow the predetermined size of the register file.